ZH
48MHz Cortex-M0+ 32-bit CPU
Supports single-cycle multiply instructions
64KBFlash, 16KB SRAM
1KB OTP
Flexible power management mode
– Auto switching of VBAT backup power
– 0.9μA VBAT mode + RTC + backup register
– 1μA Stop mode, CPU + SRAM hold mode
– 1.3μA Stop mode + RTC
Power monitoring: supports BOR and PVD
Clock source
– External high-speed clock: 4~32MHz, supports oscillation stop detection
– External low-speed clock: 32.768KHz, supports oscillation stop detection
– Internal high-speed clock: 16MHz, full temperature change ≤ ±2%
– Internal low-power low-speed clock: 32KHz
– PLL: 6MHz ~ 48MHz
Up to 57 IOs, anti-backflow and compatible with 5V communications; up to 20mA for IO with high drive capability
2-channel DMA controller with flexible mapping
RTC supports alarm clock and cycle timer,with calibration accuracy of ±0.477ppm
9x timers
– 3x 16-bit 4-channel general timers
– 1x 16-bit basic timer
– 2x 16-bit low-power timers, one of which supports orthogonal encoding
– 1x 24-bit SysTick
– 2x watchdogs: IWDG and WWDG
IRTIM supports timers and U(S)ART interconnection for infrared control
Communication interface
– 2x LPUART interfaces, supports wakeup from Stop mode
– 4x U(S)ART interfaces, one of which supports ISO7816 and SPI master mode; 3x UART interfaces
– 2x SPI interfaces, with maximum speed of 20Mbps in master mode and 16Mbps in slave mode
– 1x I2C, supports master and slave modes, 1Mbps Fm+ and wakeup from Stop mode
Information security
– AES algorithm coprocessor
– TRNG, CRC
– TAMP anti-tamper and backup registers
LCD supports up to 8COM x 32SEG
– Charge pump mode: strong drive capability, VLCD boost voltage can be higher than VDD and does not varies with VDD; VLCD can be configured in multiple levels up to 5.25V
– On-chip resistor voltage dividing mode: Contrast is adjustable in 16 levels, high and low drive capacity can be switched dynamically, and no external capacitor is required
12-bit 1Msps high-precision SAR ADC, capable of measuring signals with high output impedance
2x ultra-low power comparators with 6-bit DAC comparison reference and rail-to-rail input supported
Built-in reference voltage source VREFBUF: 3.0V, 2.5V, 2.048V, supports output through IO
1x temperature sensor, with maximum error of ±2°C
96-bit unique ID
Built-in Bootloader: supports UART
SWD debugging
Operating conditions: 1.8V~5.5V, -40°C~85°C
Package: LQFP64/48, QFN32，SSOP24
Core and system
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